K4N51163QC-ZC Datasheet, PDF (13/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
2. gDDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
VDDQ
DUT
DQ
DQS
DQS
Output
Timing
reference
25Ω
point
<AC Timing Reference Load>
V_TT = V_DDQ/2
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. gDDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
DQS, DQS ^Output
Test point
25Ω
<Slew Rate Test Load>
V_TT = V_DDQ/2
4. Differential data strobe
gDDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
DQS/
DQS
t_DQSH
t_DQSL
DQS
DQS
t_WPRE
t_WPST
DQ
DM
V_IH(ac)
V_IH(dc)
D
D
D
V_IL(ac)
t_DS
V_IH(ac) ^tDS
V_IL(dc)
t_DH
DMin
DMin
DMin
V_IL(ac)
<Data input (write) timing>
D
t_DH
V_IH(dc)
DMin
V_IL(dc)
t_CH
t_CL
CK
CK/CK
CK
DQS/DQS
DQ
DQS
DQS
t_RPRE
t_DQSQmax
Q
t_QH
Q
Q
t_DQSQmax
<Data output (read) timing>
t_RPST
Q
t_QH
- 13 -
Rev 1.5 Oct. 2005