K4N51163QC-ZC Datasheet, PDF (36/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Burst Read Command
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The
address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to
(AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle
must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for
write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or
8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the
burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR).
gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10K ohm
resistor to insure proper operation.
CK
DQS
DQ
t_CH
t_CL
CK
CK
DQS
DQS
t_RPRE
t_DQSQmax
Q
t_QH
t_RPST
Q
Q
Q
t_DQSQmax
t_QH
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Posted CAS
READ A
NOP
DQS
DQs
AL = 2
NOP
NOP
NOP
RL = 5
CL =3
NOP
=< t_DQSCK
NOP
NOP
DOUTA₀DOUTA₁DOUTA₂DOUTA₃
NOP
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Rev 1.5 Oct. 2005