K4N51163QC-ZC Datasheet, PDF (20/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Basic Functionality
Read and write accesses to the gDDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst
length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by
a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command
are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued.
Prior to normal operation, the gDDR2 SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
gDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT^*1 at a low state (all other inputs may be undefined.) The
power voltage ramps are without any slope reversal, ramp time must be no greater than 20mS; and during the ramp,
VDD>VDDL>VDDQ and VDD-VDDQ<0.3 volts.
- VDD^*2, VDDL^*2 and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95 V max, AND
- Vref tracks VDDQ/2.
or
- Apply VDD^*2 before or at the same time as VDDL.
- Apply VDDL^*2 before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & V_REF.
at least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200µs after stable power and clock(CK, CK), then apply NOP or deselect & take CKE high.
4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.
5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0, “High” to BA1.)
6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “High” to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and A12.)
8. Issue a Mode Register Set command for “DLL reset”^*2.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without
resetting the DLL.
12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).
If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit com-
mand (A9=A8=A7=0) must be issued with other operating parameters of EMRS.
13. The gDDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, V_REF must be valid and a low level must be applied to the ODT pin.
*2) If DC voltage level of V_DDL or V_DD is intentionally changed during normal operation, (for example, for the purpose of V_DD corner test, or power
saving) “DLL Reset” must be executed.
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Rev 1.5 Oct. 2005