K4N51163QC-ZC Datasheet, PDF (58/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Input Clock Frequency Change during Precharge Power Down
gDDR2 SDRAM input clock frequency can be changed under following condition :
gDDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2
clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change
only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change,
ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to
DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending
on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock
period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
Clock Frequency Change in Precharge Power Down Mode
T0
T1
CK
CK
CMD
NOP
CKE
ODT
tRP
tAOFD
T2
T4
Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Ty+4
Tz
NOP
Frequency Change
Occurs here
NOP
NOP
DLL
RESET
NOP
Valid
200 Clocks
Minimum 2 clocks
required before
changing frequency
tXP
Stable new clock
before power down exit
ODT is off during
DLL RESET
No Operation Command
The No Operation Command should be used in cases when the gDDR2 SDRAM is in an idle or a wait state. The purpose of the No
Operation Command (NOP) is to prevent the gDDR2 SDRAM from registering any unwanted commands between operations. A No
Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation
Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought
high at the rising edge of the clock, the RAS, CAS, and WE signals become don’t cares.
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Rev 1.5 Oct. 2005