K4N51163QC-ZC Datasheet, PDF (59/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Command Truth Table
Function
CKE
Previous Current ^CS
Cycle Cycle
(Extended) Mode Register Set
H
H
L
Refresh (REF)
H
H
L
Self Refresh Entry
H
L
L
Self Refresh Exit
H
L
H
L
Single Bank Precharge
H
H
L
Precharge all Banks
H
H
L
Bank Activate
H
H
L
Write
H
H
L
Write with Auto Precharge
H
H
L
Read
H
H
L
Read with Auto-Precharge
H
H
L
No Operation
H
X
L
Device Deselect
H
X
H
Power Down Entry
H
H
L
L
Power Down Exit
H
L
H
L
RAS
L
L
L
X
H
L
L
L
H
H
H
H
H
X
X
H
X
H
CAS
WE
BA0
BA1
A11
A10 A9 - A0 Note
L
L BA
OP Code
1,2
L
HX
X
X
X
1
L
HX
X
X
X
1,8
X
X
X
X
X
X
1,7
H
H
H
L BA
X
L
X
1,2
H
L
X
X
H
X
1
H
H BA
Row Address
1,2
L
L BA Column L Column 1,2,3
L
L BA Column H Column 1,2,3
L
H BA Column L Column 1,2,3
L
H BA Column H Column 1,2,3
H
HX
X
X
X
1
X
XX
X
X
X
1
X
X
X
X
X
X
1,4
H
H
X
X
X
X
X
X
1,4
H
H
Note :
1. All gDDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write"
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
8. VREF must be maintained during Self Refresh operation.
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Rev 1.5 Oct. 2005