K4N51163QC-ZC Datasheet, PDF (24/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
EMRS (1) Programming
512M gDDR2 SDRAM
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
Qoff
0
DQS
OCD Program
Rtt
Additive Latency
Rtt D.I.C DLL
BA1
0
0
1
1
BA0
0
1
0
1
MRS mode
MRS
EMRS(1)
EMRS(2): Reserved
EMRS(3): Reserved
A10 DQS
0 Enable
1 Disable
A6 A2 Rtt (NOMINAL)
0 0 ODT Disabled
01
75 ohm
10
150 ohm
11
50 ohm
A0 DLL Enable
0
Enable
1
Disable
A10
(DQS Enable)
0 (Enable)
1 (Disable)
Strobe Function
Matrix
DQS
DQS
DQS
DQS
DQS
Hi-z
A1
Output Driver
Impedance Control
Driver
Size
0
Normal
100%
1
Weak
60%
A12
Qoff (Optional)^a
0 Output buffer enabled
1 Output buffer disabled
a. Outputs disabled - DQs, DQSs, DQSs .
This feature is used in conjunction with
dimm IDD meaurements when IDDQ is
not desired to be included.
A9 A8 A7 OCD Calibration Program
0
0
0
OCD Calibration mode exit;
maintain setting
001
Drive(1)
010
Drive(0)
100
Adjust mode^a
1 1 1 _{OCD Calibration default} ^b
a: When Adjust mode is issued, AL from previously
set value must be applied.
b: After setting to default, OCD mode needs to be
exited by setting A9-A7 to 000. Refer to the follow-
ing 3.2.2.3 section for detailed information.
A5 A4 A3 Additive Latency
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5^a
1
1
0
Reserved
1
1
1
Reserved
a. AL 5 option is available only for 256Mb gDDR2.
- 24 -
Rev 1.5 Oct. 2005