K4N51163QC-ZC Datasheet, PDF (53/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Power-Down
Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not allowed to go
low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low
while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down IDD
spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into
power down.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for
proper read operation. DRAM design guarantees it’s DLL in a locked state with any CKE intensive operations as long as DRAM control-
ler complies with DRAM specifications. Following figures show two examples of CKE intensive applications. In both examples, DRAM
maintains DLL in a locked state throughout the period.
<Example of CKE instensive environment 1>
CK
CK
CKE
tCKE
tCKE
tCKE
tCKE
tCKE
DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation
<Example of CKE Iintensive enviroment 2>
CK
CK
CKE
tXP
CMD
REF
tXP
REF
tREFI = 7.8 us
The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all DRAM
guarantees all AC and DC timing & voltage specifications and DLL operation with temperature and voltage drift.
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Rev 1.5 Oct. 2005