K4N51163QC-ZC Datasheet, PDF (23/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
gDDR2 SDRAM Extended Mode Register Set
EMRS(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and addi-
tive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after
power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0, while
controlling the states of address pins A0 ~ A12. The gDDR2 SDRAM should be in all bank precharge with CKE already high prior to writ-
ing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write opera-
tion to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements
during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a
half strength data-output driver. A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used
for OCD control, A10 is used for DQS# disable.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal oper-
ation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-
enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a
Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchro-
nization to occur may result in a violation of the tAC or tDQSCK parameters.
EMRS(2)
The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined,
therefore the extended mode register(2) must be written after power-up for proper operation. The extended mode register(2) is written
by asserting low on CS, RAS, CAS, WE, high on BA1 and low on BA0, while controlling the ststes of address pins A0 ~ A15. The gDDR2
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(2). The mode register set
command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents
can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the pre-
charge state.
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Rev 1.5 Oct. 2005