K4N51163QC-ZC Datasheet, PDF (25/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
EMRS (2) Programming
512M gDDR2 SDRAM
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 _{Address Field}
1 ₀^*1
0^*1
SRF
0^*1
PSAR^*2
Extended Mode Register(2)
BA1
0
0
1
1
BA0
MRS mode
0
MRS
1
EMRS(1)
0
EMRS(2)
1 EMRS(3): Reserved
A7 High Temperature Self-Refresh Rate Enable
1
Enable
0
Disable
A2 A1 A0 Partial Array Self Refresh for 4 Banks
000
Full array
001
Half Array(BA[1:0]=00&01)
010
Quarter Array(BA[1:0]=00)
011
Not defined
100
3/4 array(BA[1:0]=01, 10&11)
101
Half array(BA[1:0]=10&11)
110
Quarter array(BA[1:0]=11)
111
Not defined
*1 : The rest bits in EMRS(2) is reserved for future use and all bits except A0, A1, A2, A7and BA0, BA1, must be programmed
to 0 when setting the mode register during initialization.
.
*2 : If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be
loast if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command
is issued. PASR is supported from the device of 90nm technology(512Mb C-die).
EMRS (3) Programming : Reserved^*1
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 _{Address Field}
11
0^*1
Extended Mode Register(3)
*1 : All bits in EMRS(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the
mode register during initialization.
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Rev 1.5 Oct. 2005