K4N51163QC-ZC Datasheet, PDF (38/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Post CAS
READ A0
NOP
Post CAS
READ A4
NOP
NOP
DQS
DQs
AL = 2
RL = 5
CL =3
NOP
NOP
NOP
NOP
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃ DOUT A₄ DOUT A₅ DOUT A₆
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4
clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed.
Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)
CK/CK
CMD ^{Read A}
DQS/DQS
DQs
NOP
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
Notes:
1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited.
3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited.
4. Read burst interruption is allowed to any bank inside DRAM.
5. Read burst with Auto Precharge enabled is not allowed to interrupt.
6. Read burst interruption is allowed by another Read with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, Minimum Read to
Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt).
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Rev 1.5 Oct. 2005