K4N51163QC-ZC Datasheet, PDF (41/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
Seamless Burst Write Operation: RL = 5, WL = 4, BL=4
512M gDDR2 SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Post CAS
WRITE A0
NOP
Post CAS
WRITE A1
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ’s
WL = RL - 1 = 4
DIN A₀ DIN A₁ DIN A₂ DIN A₃ DIN A₀ DIN A₁ DIN A₂ DIN A₃
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks
for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Writes intrrupted by a write
Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt is not allowed.
Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
CK/CK
CMD ^NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
Notes:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum Write to
Precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
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Rev 1.5 Oct. 2005