K4N51163QC-ZC Datasheet, PDF (4/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
4.0 PIN CONFIGURATION
Normal Package (Top View)
512M gDDR2 SDRAM
1
2
3
VDD
UDQ6
VDDQ
UDQ4
VDD
LDQ6
VDDQ
LDQ4
VDDL
NC
VSS
VDD
NC
VSSQ
UDQ1
VSSQ
NC
VSSQ
LDQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
VSS
UDM
VDDQ
UDQ3
VSS
LDM
VDDQ
LDQ3
VSS
WE
BA1
A1
A5
A9
NC
7
8
9
A
VSSQ UDQS
VDDQ
B
UDQS
VSSQ
UDQ7
C
VDDQ
UDQ0
VDDQ
D
UDQ2
VSSQ
UDQ5
E
VSSQ LDQS
VDDQ
F
LDQS
VSSQ
LDQ7
G
VDDQ
LDQ0
VDDQ
H
LDQ2
VSSQ
LDQ5
J
VSSDL CK
VDD
K
RAS
CK
ODT
L
CAS
CS
M
A2
A0
VDD
N
A6
A4
P
A11
A8
VSS
R
NC
NC
Note : VDDL and VSSDL are power and ground for the DLL. lt is recommended that
they are isolated on the device from VDD, VDDQ, VSS, and VSSQ.
Ball Locations
: Populated Ball
+ : Depopulated Ball
Top View
(See the balls through the Package)
123456789
A
+++
B
+++
C
+++
D
+++
E
+++
F
+++
G
+++
H
+++
J
+++
K₊
+++
L
+++
+
M₊
+++
N
+++
+
P₊
+++
R
+++
+
-4-
Rev 1.5 Oct. 2005