K4N51163QC-ZC Datasheet, PDF (27/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by gDDR2 SDRAM
and drive of DQS is dependent on EMRS bit enabling DQS operation. In Drive(1) mode, all DQ, DQS signals are driven high and all DQS
signals are driven low. In drive(0) mode, all DQ, DQS signals are driven low and all DQS signals are driven high. In adjust mode, BL = 4
of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value
of 18 ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in
section 6. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output
driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not
applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to adjust
OCD characteristics must specify A9-A7 as '000' in order to maintain the default or calibrated value.
Off- Chip-Driver program
A9 A8 A7
Operation
0 0 0 OCD calibration mode exit
0 0 1 Drive(1) DQ, DQS high and DQS low
0 1 0 Drive(0) DQ, DQS low and DQS high
1 0 0 Adjust mode
1 1 1 OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to gDDR2
SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and
controllers must drive this burst code to all DQs at the same time. DT0 in the following table means all DQ bits at bit time 0, DT1 at bit
time 1, and so forth. The driver output impedance is adjusted for all gDDR2 SDRAM DQs simultaneously and after OCD calibration, all
DQs of a given gDDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and
when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16 step
range. When Adjust mode command is issued, AL from previously set value must be applied.
Off- Chip-Driver program
4bit burst code inputs to all DQs
Operation
D_T0
D_T1
D_T2
D_T3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
NOP (No operation)
NOP (No operation)
0
0
0
1
Increase by 1 step
NOP
0
0
1
0
Decrease by 1 step
NOP
0
1
0
0
NOP
Increase by 1 step
1
0
0
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
Increase by 1 step
0
1
1
0
Decrease by 1 step
Increase by 1 step
1
0
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the following timing diagram. For
input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by MRS addressing mode (ie. sequential or interleave).
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Rev 1.5 Oct. 2005