K4N51163QC-ZC Datasheet, PDF (34/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Posted CAS
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read
cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. gDDR2 SDRAM supports 4 bit
burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address order-
ing is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the
address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported.
Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8
mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write.
Therefore the Burst Stop command is not supported on gDDR2 SDRAM devices.
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
-1 0 1 2
34
56
7
8 9 10 11 12
CK/CK
CMD
DQS/DQS
DQ
Active Read
A-Bank A-Bank
AL = 2
Write
A-Bank
CL = 3
> = tRCD
RL = AL + CL = 5
> = tRAC
WL = RL -1 = 4
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2Din3
Example 2 Read followed by a write to the same bank
[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
-1 0 1 2
34
56
7
8 9 10 11 12
CK/CK
CMD
DQS/DQS
DQ
Active
A-Bank
> = tRCD
AL = 0
Read
A-Bank
CL = 3
RL = AL + CL = 3
> = tRAC
Write
A-Bank
WL = RL -1 = 2
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2Din3
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Rev 1.5 Oct. 2005