K4N26323AE Datasheet, PDF (36/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Note 1 :
- The JEDEC DDR-II specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output valid window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL7, BL4)
0
1
CK, CK
CS
DQS
DQ
tHP
6
7
8
9
tDQSQ(max)
tQH
tDQSQ(max)
Da0
Da1
Da2
Da3
COMMAND _READA
- 36 -
Rev. 1.7 (Jan. 2003)