K4N26323AE Datasheet, PDF (32/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
4.5
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_18 In/Out)
Recommended operating conditions (Voltage referenced to VSS=0V, Tj=0 to 100°C)
Parameter
Device Supply voltage
Symbol
Min
VDD
2.4
Typ
Max
2.5
2.6
Output Supply voltage
Reference voltage
VDDQ
1.7
1.8
1.9
VREF
0.49*VDDQ
-
0.51*VDDQ
DC Input logic high voltage
VIH (DC)
VREF+0.125
-
VDDQ+0.30
DC Input logic low voltage
VIL (DC)
-0.30
-
VREF-0.125
AC Input logic high voltage
VIH(AC)
VREF+0.25
-
-
AC Input logic low voltage
Output logic high voltage
VIL(AC)
VOH
-
Vtt+0.4
-
VREF-0.25
-
-
Output logic low voltage
VOL
-
Input leakage current
IIL
-5
Output leakage current
IOL
-5
-
Vtt-0.4
-
5
-
5
Unit
V
V
V
V
V
V
V
V
V
uA
uA
Note
1
1
2
4
5
6
6
7
7
Note : 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. Output logic high voltage and low voltage is depend on channel condition.(Ract , Ron)
7. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V
- 32 -
Rev. 1.7 (Jan. 2003)