K4N26323AE Datasheet, PDF (19/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Seamless Burst Write Operation : AL = 1, CL = 7, WL = AL + 1 = 2
0
1
2
3
7
8
9
10
11
CK, CK
CMD
Post CAS
WRITE A
NOP
Post CAS
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ’s
WL = 2
DINA₀ DINA₁ DINA₂ DINA₃ DINB₀ DINB₁ DINB₂ DINB₃
The seamless burst write operation is supported by enabling a write command every other clock.
This operation is allowed regardless of same or different banks as long as the banks are activated
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Rev. 1.7 (Jan. 2003)