K4N26323AE Datasheet, PDF (11/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of GDDR2 SDRAM. It programs CAS
latency, addressing mode, test mode and various vendor specific options to make GDDR2 SDRAM useful for variety of dif-
ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after
EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR2
SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum
four clock cycles are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing
mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is used for test mode. A9 ~ A11 are
used for tWR. Refer to the table for specific codes for various addressing modes and CAS latencies.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0
0
tWR
0 TM
CAS Latency
BT
Burst Length
Mode Register
*
Test Mode
Burst Length ^*1
A7 mode
A2 A1 A0 Burst Length
BA0
An ~ A0
0 Normal
010
4
0
MRS
1
Test
Burst Type
1
EMRS
0
A3
Burst Type
0
Sequential
tWR
A11 A10 A9
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MRS Select
Reserved
Reserved
3
4
5
Reserved
Reserved
Reserved
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserved
Reserved
Reserved
Reserved
Reserved
5
6
7
*1. BL 4, Sequential Only
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Rev. 1.7 (Jan. 2003)