K4N26323AE Datasheet, PDF (27/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
On-Die Termination
All pins except ZQ, CKE Pins adopt on-die termination to improve signal integrity of channel. The On-Die Termination
should be controlled by EMRS command at low frequency clock (<100Mhz). The On-Die Termination control command
should be issued before issuing DLLON command by EMRS or simultaneously to guarantee stable channel condition of
/CK and CK pins. If A3, A2 = 0, 0, the On-Die Termination of all pins will be deactivated. If A3, A2 = 0, 1, the On-Die
Termination will be self-calibrated by detecting the external Resistor on ZQ pin. If A3, A2 = 1, 0, the value of the On-Die
Termination of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and 4DQS pins will be the fixed value, 60ohm. If A3, A2 = 1, 1, the
value of the On-Die Termination of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and 4DQS pins will be the fixed value,120ohm.
If A3, A2 = 0, 1 is issued by EMRS, the value of the on-die termination of each pin is determined by monitoring the
value of a external resistor which is connected between ZQ pin and VSSQ, and updated every CBR refresh cycle to
compensate variation of voltage and temperature.
The value of On-Die Termination of CMD and ADD (/RAS, /CAS, /WE, /CS, BA0, BA1 and A0 ~ A11) pins of each
DRAM depend on EMRS code (A1, A0). If A1, A0 = 0, 0 , the On-die Termination of CMD and ADD pins will be deacti-
vated. If A1, A0 = 0, 1, the value of the On-die Termination of CMD and ADD pins will be same value as the value of
DQ pins. If A1, A0 = 1, 0, the value of the On-Die Termination of CMD and ADD pins will be two times of the value of
DQ pins. If A1, A0 = 1, 1, the value of the On-Die Termination of CMD and ADD pins will be four times of the value of
DQ pins.
The On-Die Termination for one bank system with self-calibration code (A3, A2 = 0, 1)
The value of external resistor (Rref) at external one bank system is 2 times of target termination value of DQ’s on chan-
nel (Rterm). Then the value of On-Die Termination of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and 4DQS pins is half value
of the external resistor. The value of On-Die Termination of CMD and ADD ( /RAS, /CAS, /WE, /CS, BA0, BA1 and A0
~ A11) pins of each DRAM depend on EMRS code (A2, A0).
The following figure shows the typical external one bank system having on-die termination.
Block Diagram of 1 Bank System
Front Side DRAMs
CK,/CK
ADD
/RAS,/CAS,/WE,/CS
DM’s, DQ’S,
DQS’s,/DQS’s
CK,/CK
DM’s, DQ’S,
DQS’s,/DQS’s
CK,/CK
/CS
/RAS,/CAS,/WE
DM’s, DQ’S,
DQS’s,/DQS’s
CK,/CK
DM’s, DQ’S,
DQS’s,/DQS’s
CK,/CK
ZQ
ADD
/RAS,/CAS,/WE,/CS
DM’s, DQ’S,
DQS’s,/DQS’s
Rref=2 X Rterm
VSSQ
CK,/CK
ZQ
ADD
/RAS,/CAS,/WE,/CS
DM’s, DQ’S,
DQS’s,/DQS’s
2XRterm
VSSQ
CK,/CK
ZQ
ADD
/RAS,/CAS,/WE,/CS
DM’s, DQ’S,
DQS’s,/DQS’s
2XRterm
VSSQ
CK,/CK
ZQ
ADD
/RAS,/CAS,/WE,/CS
2XRterm
DM’s, DQ’S,
DQS’s,/DQS’s
VSSQ
Where Rterm is the termination value on charnnel
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Rev. 1.7 (Jan. 2003)