K4N26323AE Datasheet, PDF (3/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Revision 0.5 (January 2002)
- Eliminated DLLEN pin
- Power-up sequence
Revision 0.4 (January 2002)
- Changed EMRS Table
- Changed Self-Refresh exit mode
- Changed On-die Termination Control
- Changed OCD Control method
- Power-up sequence
Revision 0.3 (December 2001)
- Noted the ball names changed from DDR-1 and exchanged DQS and /DQS ball location.
- Added On-die termination control
- Changed OCD align mode entry / exit timing
- Added target value of Data & DQS input/output capacitance(DQ0~DQ31)
- Added Table for auto precharge control
- Typo corrected.
Revision 0.2 (November 2001)
- Data Strobe Scheme is changed from DQS separation of Read DQS, Write DQS to Differential and Bi-directional DQS
- OCD adjustment
- Controlled DQ is changed from DQ0, WDQS2 to DQ23, DQS2 and /DQS2
Revision 0.1 (October 2001)
- Data Strobe Scheme is changed from Bi-directional DQS to DQS separation to Read DQS, Write DQS
- Package Ball layout is changed for mirror package.
- OCD adjustment
Controlled DQ is changed from DQ0, DQS0 to DQ23, WDQS2
- Added DM descriptions
- 1bank, 2bank system
- Added System Selection mode in EMRS table.
Revision 0.0 (August 2001)
-3-
Rev. 1.7 (Jan. 2003)