K4N26323AE Datasheet, PDF (15/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in GDDR2
SDRAM. In this operation, the GDDR2 SDRAM allows a CAS read or write command to be issued tRCDmin or 1 tCK ear-
lier than tRCDmin after the RAS bank activate command. The command is held for the time of the Additive Latency (AL)
before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL).
Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into
the EMRS.
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank
[AL = 1, t_RCD = 9, CL = 7, RL = (AL + CL) = 8, WL = (AL + 1) = 2]
0
7
8
13 14 15 16 17 18 19 20 21 22 23
CK, CK
CMD
Active
A-Bank
DQS
Read
A-Bank
t_RL
Write
A-Bank
DQ
t_WL
Dout0 Dout1 Dou2 Dout3
t_HZ
Din0 Din1 Din2 Din3
tHZ > 1 tCK
Example 2 Read followed by a write to the same bank
[AL = 0, t_RCD = 9, CL = 7, RL = (AL + CL) = 7, WL = (AL + 1) = 1]
0
1
8
9
14 15 16 17 18 19 20 21 22
CK, CK
CMD
Active
A-Bank
Read
A-Bank
RL
Write
A-Bank
DQS
DQ
t_RCD
Dout0 Dout1 Dout2 Dout3
t_WL
Din0 Din1 Din2 Din3
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Rev. 1.7 (Jan. 2003)