K4N26323AE Datasheet, PDF (25/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Automatic Refresh Command (CAS Before RAS Refresh)
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Automatic Refresh
mode (CBR). All banks of the GDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (t_RP)
before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device, supplies the bank
address during the refresh cycle. No control of the external address bus is required once this cycle has started.
When the refresh cycle has completed, all banks of the GDDR2 SDRAM will be in the precharged (idle) state. A delay
between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command
must be greater than or equal to the Auto Refresh cycle time (t_RFC).
CK, CK
CKE
CMD ^Precharge
High
> = t_RP
NOP
> = t_RFC
CBR
Bank
Activate
NOP
NOP
Self Refresh Command
The GDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by
having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the Self Refresh Command is registered,
CKE must be held low to keep the device in Self Refresh mode and NOP command should be issued or CS should be held high to
ensure stable self refresh operation for next four cycles after the Self Refresh Command. When the GDDR2 SDRAM has entered Self
Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh
Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be
restarted before the device can exit Self Refresh operation. After CKE is brought high, an internal timer is started to insure CKE is
held high for approximately 10ns before registering the Self Refresh exit command. The purpose of this circuit is to filter out noise
glitches on the CKE input which may cause the GDDR2 SDRAM to erroneously exit Self Refresh operation. Once the Self Refresh
exit command is registered, a delay equal or longer than the tXSA (>20000 tck) must be satisfied before any command can be issued
to the device. CKE must remain high for the entire Self Refresh exit period (tXSA > 20000tCK) and commands must be gated off with
CS held high. Alternatively, NOP commands may be registered on each positive clock edge during the Self Refresh exit interval. (See
Figure.)
CK, CK
CKE
CMD
Self Refresh
tXSA (> 20000tCK)
> = 4clk
NOP
NOP
ANY
Command
*After self refresh entry, NOP or chip deselect command should be issued during more than 4 cycles
and chip deselet command should be issued for tXSA after self refresh exit.
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Rev. 1.7 (Jan. 2003)