K4N26323AE Datasheet, PDF (21/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Burst Read Operation Followed by Precharge: RL = 8 (AL=1, CL=7, t_RP =8)
0
3
7
8
9
10
11
12
13
CK, CK
CMD
Posted CAS
READ A
Precharge A
NOP
NOP
NOP
NOP
Bank A
Activate
NOP
NOP
DQS
DQ’s
RL = 8
> = t_RP
DOUTA₀ DOUTA₁ DOUTA₂ DOUTA₃
Burst Write followed by Precharge
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command
can be issued. This delay is known as a write recovery time (t_WR) referenced from the completion of the burst write to the
precharge command. No Precharge command should be issued prior to the tWR delay, as GDDR2 SDRAM does not sup-
port any burst interrupt operation.
Burst Write followed by Precharge: AL = 1, CL = 7, WL = AL + 1 = 2, t_WR = 5
0
1
2
3
4
5
6
9
CK, CK
CMD ^{Posted CAS}
WRITE A
NOP
DQS
DQ’s
WL = 2
NOP
NOP
NOP
DINA₀ DINA₁ DINA₂ DINA₃
NOP
NOP
NOP
Precharge A
t_WR = 5
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Rev. 1.7 (Jan. 2003)