K4N26323AE Datasheet, PDF (18/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Burst Write Operation
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the
clock. The address inputs determine the starting column address. Write latency (WL) is defined by an Additive
Latency(AL) plus one and is equal to (AL + 1). The first data bit of the burst cycle must be applied to the DQ pins at the
first rising edge of the clock and at the first falling edge of the clock. The tDQSS specification must be satisfied for write
cycles. The subsequent burst bit data are issued on successive edges of the clock until the burst length of 4 is com-
pleted. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is
ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is
the write recovery time (tWR).
Burst Write Operation : AL= 1, CL = 7, WL = 2, t_WR = 5
0
1
2
3
4
5
6
9
CK, CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
DQS
DQ
WL =2
DINA₀ DINA₁ DINA₂ DINA₃
tWR = 5
Burst Write followed by Burst Read : RL = 7 (AL=0, CL=7), WL = 1, tCDLR = 4
0
1
2
3
7
14
15
16
CK, CK
Write to Read Latency = WL + 2 + t _CDLR =7
CMD
Post CAS
WRITE A
NOP
NOP
NOP
NOP
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
DQS
DQ
tWL = 1
DINA₀ DINA₁ DINA₂ DINA₃
> = tCDLR
CL = 7
DOUTA₀ DOUTA₁ DOUTA₂ DOUTA₃
The minimum number of clock from the burst write command to the burst read command is WL+2+a write-to-
read-turn-around-time(tCDLR).
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Rev. 1.7 (Jan. 2003)