K4N26323AE Datasheet, PDF (10/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Power-Up Sequence
GDDR2 SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Power Up Sequence
- Apply Power and Keep CKE at low state. (All other inputs may be undefined)
- Apply VDD before VDDQ.
- Apply VDDQ before VREF.
- Start low frequency clock(100MHz) and maintain stable condition for minimum 200us.
- The minimum of 200us after stable power and clock (CK, /CK), apply NOP and take CKE to be high.
- Issue precharge command for all banks of the device ( tS/tH =0.5tCK).
- Issue EMRS command to initialize DRAM with DLL OFF and On-die Termination OFF( tS/tH=0.5tCK) .
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Bus}
Extended Mode
010X
X
0
X
00
X
Register
- Issue EMRS command to control DLL and decide on-die termination state.
Within 100 clocks after issuing EMRS command for DLL on, stable high frequency clock should be supplied to DRAM.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Bus}
Extended Mode
010V
V
1
V
VV
V
Register
(V=Valid value)
- The additional 1ms clock cycles are required to lock the DLL and determine value of on-die termination after issuing
EMRS command or supplying stable clock from a controller.
Apply NOP during Locking DLL to protect invalid command.
- Issue precharge command for all banks of the device.
- Issue EMRS command
- Issue at least 10 or more Auto refresh command to update the value of on-die termination.
- Issue a MRS command to initialize the mode register.
- Issue any command.
Power up & Initialization Sequence
CKE
CK,CK
200 us
< 100tCK
1ms
low freq. (> 100Mhz)
stable high freq.
tRP
tRP tMRD ^tRFC
tRFC
CMD
NOP
Precharge NOP
all banks
EMRS1 NOP EMRS2
NOP
Precharge
all banks
EMRS 1st Auto
Refresh
10th Auto
Refresh
MRS
* Minimum setup/hold time tIS, tIHmin = 0.5tCK at the Low frequency without DLL
* Within 100 tCK after issuing EMRS2, PLL(DLL) of controller should be enabled.
* During changing clock frequency, the changing rate should be smaller than 100ps/30tCK
4 Clock min.
Any
Command
- 10 -
Rev. 1.7 (Jan. 2003)