K4N26323AE Datasheet, PDF (30/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
4. Command Truth Table.
Function
CKE
Previous Current ^CS
Cycle
Cycle
Mode Register Set
H
X
L
Extended Mode Register Set
H
X
L
Auto (CBR) Refresh
H
H
L
Entry Self Refresh
H
L
L
Exit Self Refresh
L
H
H
L
H
L
Single Bank Precharge
H
X
L
Precharge all Banks
H
X
L
Bank Activate
H
X
L
Write
H
X
L
Write with Auto Precharge
H
X
L
Read
H
X
L
Read with Auto-Precharge
H
X
L
DM
H
X
X
No Operation
H
X
L
H
X
H
H
Power Down Mode Entry
H
L
H
L
L
Power Down Mode Exit
L
H
H
L
H
L
RAS CAS WE DM BA0/BA1 A11 - A9 A8 A7 - A0 Notes
L
L
L
X
BA0 = 0 and MRS OP Code
1
L
L
L
X
BA0 = 1 and EMRS OP Code
1
L
L
H
X
X
X
X
X
1
L
L
H
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
H
H
H
X
X
X
X
X
L
H
L
X
BA
X
L
X
1,2
L
H
L
X
X
X
H
X
1
L
H
H
X
BA
Row Address
1,2
H
L
L
X
BA
X
L Column 1,2,3,
H
L
L
X
BA
X
H Column 1,2,3,
H
L
H
X
BA
X
L Column 1,2,3
H
L
H
X
BA
X
H Column 1,2,3
X
X
X
DM
X
X
X
X
6
H
H
H
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1,4,5
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
1,4,5
H
H
H
X
X
X
X
X
1. All of the GDDR2 SDRAM operations are defined by states of CS, WE, RAS, and CAS at the positive rising edge of the clock.
2. Bank Select (BA0,1), determine which bank is to be operated upon.
3. Burst read or write cycle may not be terminated.
4. The Power Down Mode does not perform any refresh operations, therefore the device can’t remain in this mode longer than the Refresh period
(t_REF) of the device. Four clock delay is required for mode entry and exit.
5. If CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle.
6. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
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Rev. 1.7 (Jan. 2003)