K4N26323AE Datasheet, PDF (16/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the
clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to
when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe out-
put (DQS) is driven low 1 clock before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized
with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS
signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is
defined by the Mode Register Set (MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the
Extended Mode Register Set (EMRS).
Burst Read Operation: RL = 8 (AL = 1, CL = 7)
0
1
2
CK, CK
7
8
9
10
11
12
13
CMD
Posted CAS
READ A
NOP
Post CAS
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQs
AL =1
RL = 8
CL = 7
tDQSCK
DOUTA₀ DOUTA₁ DOUTA₂ DOUTA₃ DOUTA₄ DOUTA₅ DOUTA₆ DOUTA₇
internal Read
Command Start
(Bank A)
Burst Read Operation: RL = 7 (AL = 0 and CL = 7)
0
1
2
CK, CK
7
8
9
10
11
12
13
CMD
Posted CAS
READ A
NOP
Post CAS
Read A
NOP
DQS
DQs
CL = 7
RL = 7
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DOUTA₀ DOUTA₁ DOUTA₂ DOUTA₃ DOUTA₄ DOUTA₅ DOUTA₆ DOUTA₇
NOP
internal Read
Command Start
(Bank A)
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Rev. 1.7 (Jan. 2003)