K4N26323AE Datasheet, PDF (12/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data output driver strength and on-die termination options. The
extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR2
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis-
ter). The state of address pins A0 ~ A11 and BA0 in the same cycle as CS, RAS, CAS and WE going low are
written in the extended mode register. Four clock cycles are required to complete the write operation in the
extended mode register. 8 kinds of the output driver strength are supported by EMRS (A9, A8, A7) code. The
mode register contents can be changed using the same command and clock cycle requirements during opera-
tion as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Extended
0
1
0 ODT.R Output driver strength DLL DQS A.L ODT control ODT option _{Mode Register}
BA0
An ~ A0
0
MRS
1
EMRS
ODT of DQs @ RD
A10
mode
0
ON
1
OFF
Output Driver Strength Option
A9 A8 A7 Ron[ohm]
000
60
001
55
010
50
011
45
100
40
101
35
110
30
111
25
DLL ^*1
A6
DLL
0 DLLOFF
1
DLLON
DQS^*2
A5
DQS
0 Differential
1
Single
Additive Latency
A4 Latency
0
0
1
1
On-Die Termination Mode*1
A3 A2
00
01
10
Value
ODT OFF
ODT Cal. ON
Rterm=60
1 1 Rterm=120
On-die Termination option
for CMD & ADDR^*1
A1 A0 Value
00
OFF
01
X1
10
X2
11
X4
OFF : On-die Termination of CMD
and ADDR pins on DRAM is off
X1 : On-die Termination value of
CMD and ADD pins are same as
the value of DQ
X2 : 2 times of the value of DQ
X4 : 4 times of the value of DQ
*1. DLL control,ODT control,and ODT option command should be issued at low frequency clock(<100Mhz) with tIS/tIH=0.5tCK
*2. When single DQS is selected, 4 /DQS pins should be connected to VREF.
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Rev. 1.7 (Jan. 2003)