K4N26323AE Datasheet, PDF (13/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
DQS
500MHz
Differential DQS
450MHZ
Differential DQS
400MHz
Differential DQS
Single DQS
* To support existing DDR-I user , single DQS is supported under 400MHz by EMRS option, When single DQS is
selected, 4 /DQS pins should be connected to VREF.
Differntial DQS Timing (CL5, BL4)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CK, CK
CMD
DQS
DQS
READ
WRITE
DQ
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2 Din3
Single DQS Timing (CL5, BL4)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CK, CK
CMD
DQS
READ
DQS
Vref Level
WRITE
DQ
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2 Din3
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Rev. 1.7 (Jan. 2003)