K4N26323AE Datasheet, PDF (31/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
5. Clock Enable (CKE) Truth Table
Current State
Self Refresh
Power Down
All Banks Idle
CKE
Previous Current
Cycle
Cycle
H
X
L
H
L
H
L
H
L
L
H
X
L
H
L
H
L
H
L
L
H
H
H
H
H
L
H
L
H
L
H
H
Any State other
than listed
H
L
above
L
H
L
L
Command
CS RAS CAS WE
X
X
X
X
H
X
X
X
L
H
H
H
L
Command
X
X
X
X
X
X
X
X
H
X
X
X
L
H
H
H
L
Command
X
X
X
X
H
X
X
X
L
Command
H
X
X
X
L
Command except self-
refresh command
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BA1, BA0,
A11 - A0
X
X
X
Address
X
X
X
X
Address
X
Address
X
X
X
X
X
X
Action
Notes
INVALID
1
Exit Self Refresh with Device Deselect
2
Exit Self Refresh with No Operation
2
ILLEGAL
2
Maintain Self Refresh
INVALID
1
Power Down mode exit, all banks idle
2
Exit Power Down mode with No Operation 2
ILLEGAL
2
Maintain Power Down Mode
Device Deselect
3
Refer to the Current State Truth Table
3
Power Down
ILLEGAL
Entry Self Refresh
4
Refer to operations in the Current State
Truth Table
Power Down
5
Power Down
Power Down
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (t_CES) must be
satisfied before any command other than self refresh exit.
3. The inputs (BA1, BA0, A11 - A0) depend on the command that is issued. See the Current State Truth Table for more information.
4. The Auto Refresh, Self Refresh Mode, and the Mode Register Set modes can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
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Rev. 1.7 (Jan. 2003)