K4N26323AE Datasheet, PDF (14/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock.
The bank addresses BA0 and BA1 are used to select the desired bank. The row address A0 through A11 is used to deter-
mine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write
operation can be executed. Immediately after the bank active command, the GDDR2 SDRAM can accept a read or write
command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specifi-
cation, then additive latency must be programmed into the device to delay when the R/W command is internally issued to
the device. The additive latency value must be chosen to assure tRCDmin is satisfied.
Additive latencies of (0,1) are supported. Once a bank has been activated it must be precharged before another Bank
Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP,
respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined
by the RAS cycle time of the device (t_RC), which is equal to tRAS + tRP. The minimum time interval between Bank Acti-
vate commands, Bank 0,1, 2, 3 (in any order), is the Bank to Bank delay time (t_RRD).
Bank Activate Command Cycle : CL=7, t_RCD=9, AL=1, t_RP=8, t_RRD=5, t_CCD=2, t_RAS=19
01
CK, CK
CMD Bank A
Activate
23
t_RRD = 5
45
Bank B
Activate
DQS
DQ
t_RCD = 9
t_{RAS = 19}
89
13 14 15 16 17 18 19
24
Post CAS
Read A
Additive Latency
Post CAS
Read B
Additive Latency
Bank A
Precharge
Bank B
Precharge
t_RP = 8
CAS Latency
Dout0 Dout1 Dou2 Dout3
27
Bank A
Activate
internal Read
Command Start
(Bank A)
internal Read
Command Start
(Bank B)
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and
CAS low at the clock’s rising edge. The WE must also be defined at this time to determine whether the access cycle is a
read operation (WE high) or a write operation (WE low).
A new burst access must not interrupt the previous 4 bit burst operation. The minimum CAS to CAS delay is defined by
tCCD, and is a minimum of 2 clocks for read or write cycles.
Write Latency
The Write Latency(WL) is always defined as AL(Additive Latency)+1 where Read Latency is defined as the sum of addi-
tive latency plus CAS latency (RL=AL+CL).
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Rev. 1.7 (Jan. 2003)