K4N26323AE Datasheet, PDF (35/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
AC CHARACTERISTICS
Parameter
CL=7
CK cycle time
CL=6
CL=5
CK high width
CK low width
DQS out access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
DQS in/out high level
DQS in/out low level
Address and Control input setup
Address and Control input hold
Write command to first DQS
latching transition
Write preamble setup time
Write postamble
Write preamble
DQ_in and DM setup time to DQS
DQ_in and DM hold time to DQS
Clock half period
Data output hold time from DQS
Jitter over 1-6 clock cycles of CK
Cycle to Cycle duty cycle error
Rise and fall times of CK
Symbol
tCK
tCH
tCL
tDQSCK
tDQSQ
tRPRE
tRPST
tDQSH
tDQSL
tIS
tIH
-20 (GF1000)
Min
Max
2.0
4.0
-
-
-
-
0.45
0.55
0.45
0.55
-0.35
0.35
-0.225
0.225
0.85
1.15
0.35
0.65
0.45
0.55
0.45
0.55
0.5
-
0.5
-
-22 (GF900)
Min
Max
-
-
2.22
4.0
-
-
0.45
0.55
0.45
0.55
-0.45
0.45
-0.25
0.25
0.88
1.12
0.38
0.62
0.45
0.55
0.45
0.55
0.55
-
0.55
-
-25 (GF800)
Unit
Min
Max
-
-
ns
-
-
ns
2.5
4.0
ns
0.45
0.55 tCK
0.45
0.55 tCK
-0.45
0.45
ns
-0.28
0.28
ns
0.9
1.1
tCK
0.4
0.6
tCK
0.45
0.55 tCK
0.45
0.55 tCK
0.6
-
ns
0.6
-
ns
tDQSS WL - 0.15 WL + 0.15 WL - 0.15 WL + 0.15 WL - 0.15 WL + 0.15 tCK
tWPRES
0
-
0
-
0
-
ps
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tWPRE
0.35
-
0.35
-
0.35
-
tCK
tDS
0.25
-
0.27
-
0.3
-
ns
tDH
0.25
-
0.27
-
0.3
-
ns
tHP
tCL/H min
-
tCL/H min
-
tCL/H min
-
ns
tQH
tHP-0.225
-
tHP-0.25
-
tHP-0.28
-
ns
tJ *1
-
50
-
55
-
65
ps
tDC,ERR
-
50
-
55
-
65
ps
tR, tF
-
400
-
450
-
500
ps
1. The cycle to cycle jitter and 2~6 cycle short term jitter.
Simplified Timing @ BL=4, CL=7, AL=0
0
1
2
6
7
8
9
10
11
12
CK, CK
CMD
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
Post CAS
Write A
NOP
NOP
DQS
DQ’s
WDQS
RL = 7
DOUT A₀ DOUT A1 DOUT A2 DOUT A3
DIN A0 DIN A1 DIN A2 DIN A3
WL = 1
- 35 -
Rev. 1.7 (Jan. 2003)