K4N26323AE Datasheet, PDF (17/52 Pages) Samsung semiconductor – 128Mbit GDDR2 SDRAM

K4N26323AE-GC
128M GDDR2 SDRAM
Burst Read followed by Burst Write : AL = 1, CL = 7, RL = 8, WL = (AL+1) = 2
0
1
6
7
8
9
10
11
12
13
CK, CK
CMD
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
Post CAS
Write A
NOP
NOP
NOP
DQS
DQ’s
RL =8
tHZ
DOUTA₀ DOUTA₁ DOUTA₂ DOUTA₃
WL = 2
DINA₀ DINA₁ DINA₂ DINA₃
tHZ > 1 tCK
Seamless Burst Read Operation: CL = 7, AL = 1, RL = 8
0
1
2
CK, CK
7
8
9
10
11
Post CAS
CMD READ A0
NOP
Post CAS
READ A4
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ’s
AL = 1
RL = 8
CL =7
DOUTA₀ DOUTA₁ DOUTA₂ DOUTA₃ DOUTA₄ DOUTA₅ DOUTA₆
The seamless burst read operation is supported by enabling a read command at every other clock. This operation is
allowed regardless of same or different banks as long as the banks are activated.
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Rev. 1.7 (Jan. 2003)