HD64F7144FW50V Datasheet, PDF (90/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

2. CPU
Instruction
Instruction Code
Operation
Execution
States T Bit
TRAPA #imm
11000011iiiiiiii PC/SR → stack area, (imm × 4 + 8
—
VBR) → PC
Note: * The number of execution states before the chip enters sleep mode: The execution
states shown in the table are minimums. The actual number of states may be increased
when (1) contention occurs between instruction fetches and data access, or (2) when
the destination register of the load instruction (memory → register) equals to the
register used by the next instruction.
Rev.4.00 Mar. 27, 2008 Page 44 of 882
REJ09B0108-0400