HD64F7144FW50V Datasheet, PDF (316/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

11. Multi-Function Timer Pulse Unit (MTU)
Example of Cascaded Operation Setting Procedure: Figure 11.18 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
[2] Set the CST bit in TSTR for the upper and
lower channel to 1 to start the count
operation.
<Cascaded operation>
Figure 11.18 Cascaded Operation Setting Procedure
Examples of Cascaded Operation: Figure 11.19 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1 and phase counting mode has been
designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
0000
0001
0000
Figure 11.19 Example of Cascaded Operation
Rev.4.00 Mar. 27, 2008 Page 270 of 882
REJ09B0108-0400