HD64F7144FW50V Datasheet, PDF (182/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

8. Data Transfer Controller (DTC)
8.5 Usage Notes
8.5.1 Prohibition against DMAC/DTC Register Access by DTC
DMAC and DTC register access by the DMAC is prohibited.
8.5.2 Module Standby Mode Setting
DTC operation can be disabled or enabled using the module standby control register. The initial
setting is for DTC operation to be halted. Register access is enabled by clearing module standby
mode.
When the MSTP24 and MSTP25 bits in MSTCR1 are set to 1, the DTC clock is halted and the
DTC enters module standby mode. The MSTP24 and MSTP25 bit cannot be set to 1 during
activation of the DTC.
In addition, when the module standby mode is entered, clear all the DTER bits to 0.
For details, refer to section 24, Power-Down Modes.
8.5.3 On-Chip RAM
The DTMR, DTSAR, DTDAR, DTCRA,DTCRB and DTIAR registers are all located in on-chip
RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.
Rev.4.00 Mar. 27, 2008 Page 136 of 882
REJ09B0108-0400