HD64F7144FW50V Datasheet, PDF (437/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

12. Watchdog Timer
12.6.3 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while
the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by
clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0.
12.6.4 Changing between Watchdog Timer and Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
12.6.5 System Reset by WDTOVF Signal
If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly.
Avoid inputting the WDTOVF signal to the RES pin directly. To reset the entire system with the
WDTOVF signal, use the circuit shown in figure 12.9.
Reset input
This LSI
RES
Reset signal to entire system
WDTOVF
Figure 12.9 Example of System Reset Circuit Using WDTOVF Signal
12.6.6 Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a
TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset.
Rev.4.00 Mar. 27, 2008 Page 391 of 882
REJ09B0108-0400