HD64F7144FW50V Datasheet, PDF (218/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

10. Direct Memory Access Controller (DMAC)
10.3.4 DMA Channel Control Registers_0 to 3 (CHCR_0 to CHCR_3)
DMA channel control registers_0 to 3 (CHCR_0 to CHCR_3) are 32-bit readable/writable
registers where the operation and transmission of each channel is designated.
Bit Bit Name Initial Value R/W Description
31 ⎯
All 0
R
Reserved
to
These bits are always read as 0. The write value should
21
always be 0.
20 DI
0
(R/W)*² Direct/Indirect
Specifies either direct address mode operation or indirect
address mode operation for channel 3 source address.
This bit is valid only in CHCR_3. For CHCR_0 to
CHCR_2, this bit is always read as 0 and the write value
should always be 0.
0: Direct access mode operation for channel 3
1: Indirect access mode operation for channel 3
19 RO
0
(R/W)*² Source Address Reload
Selects whether to reload the source address initial value
during channel 2 transfer. This bit is valid only for
CHCR_2. For CHCR_0, CHCR_1, and CHCR_3, this bit
is always read as 0 and the write value should always be
0.
0: Does not reload source address
1: Reloads source address
18 RL
0
(R/W)*² Request Check Level
Selects whether to output DRAK notifying external device
of DREQ received, with active high or active low. This bit
is valid only for CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and the write value
should always be 0.
0: Output DRAK with active high
1: Output DRAK with active low
Rev.4.00 Mar. 27, 2008 Page 172 of 882
REJ09B0108-0400