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HD64F7144FW50V Datasheet, PDF (529/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 | |||
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14. I2C Bus Interface (IIC) Option
Table 14.4 The Relationship between Flags and Transfer States (Master Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State
1 1 0 0 0 0 0â 0 0â 0â 0
â¯
0
Idle state (flag clearing
required)
1 1 1â 0 0 1â 0 0 0 0 0
⯠1â
Start condition detected
1 ⯠1 0 0 ⯠0 00 0 ⯠⯠â¯
Wait state
1 1 1 0 0 ⯠0 0 0 0 1â ⯠â¯
Transmission end (ACKE = 1
and ACKB = 1)
1 1 1 0 0 1â 0 0 0 0 0
⯠1â
Transmission end with
ICDRE = 0
1 1 1 0 0 ⯠0 00 0 0
â¯
0â
ICDR write with the above
state
1 1 1 0 0 ⯠0 00 0 0
â¯
1
Transmission end with
ICDRE = 1
1 1 1 0 0 ⯠0 00 0 0
â¯
0â
ICDR write with the above
state or after start condition
detected
1 1 1 0 0 1â 0 0 0 0 0
⯠1â
Automatic data transfer from
ICDRT to ICDRS with the
above state
1 0 1 0 0 1â 0 0 0 0 ⯠1â â¯
Reception end with ICDRF =
0
1 0 1 0 0 ⯠0 0 0 0 ⯠0â â¯
ICDR read with the above
state
1 0 1 0 0 ⯠0 00 0 ⯠1
â¯
Reception end with ICDRF =
1
1 0 1 0 0 ⯠0 0 0 0 ⯠0â â¯
ICDR read with the above
state
1 0 1 0 0 1â 0 0 0 0 ⯠1â â¯
Automatic data transfer from
ICDRS to ICDRR with the
above state
0â 0â 1 0
0
â¯0
1â 0 0 â¯
â¯
â¯
Arbitration lost
1 ⯠0â 0 0 ⯠0 0 0 0 ⯠⯠0â
Stop condition detected
[Legend]
0:
0-state retained
1:
1-state retained
â¯: Previous state retained
0â: Cleared to 0
1â: Set to 1
Rev.4.00 Mar. 27, 2008 Page 483 of 882
REJ09B0108-0400
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