HD64F7144FW50V Datasheet, PDF (575/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

14. I²C Bus Interface (IIC) Option
4. The SCL and SDA inputs are sampled in synchronization with Pφ. Therefore, the AC timing
depends on the period of Pφ cycle t . _pcyc When the Pφ frequency does not reach 5 MHz, the AC
timing specifications of the I²C bus interface are not satisfied.
5. The SCL rising time t_Sr is defined as being within 1,000 ns (300 ns in the high-speed mode).
The I²C bus interface monitors SCL in the master mode, and communication is synchronized in
a bit-by-bit basis. When the rise time t_Sr (the time required to reach V_IH from an initially low
level) of SCL exceeds the time determined by the input clock of the I²C bus interface, the high-
level period of SCL is extended. The time SCL takes to rise is determined by the pull-up
resistance and the load capacitance. Therefore, to operate at the specified transfer rate, set the
pull-up resistance and load capacitance so that each time is within the corresponding value
given in table 14.9.
Table 14.9 Tolerance of the SCL Rise Time (t_Sr)
IICX
0
1
t_pcyc
7.5 t_pcyc Standard
mode
I²C bus
specification
(Max.)
1000
High-speed 300
mode
17.5
t_pcyc
Standard 1000
mode
High-speed 300
mode
Pφ=
10MHz
750
←
←
←
Time [ns]
Pφ=
16MHz
468
Pφ=
20MHz
375
←
←
←
875
←
←
Pφ=
25MHz
300
←
700
←
Pφ=
33MHz
227
227
530
←
Pφ=
40MHz
188
188
438
←
6. The rise and fall times of SCL and SDA are respectively prescribed as being 1000 ns or less
and 300 ns or less by the I²C bus specification. The output timing of SCL and SDA for the I²C
bus interface of this LSI are described by t_pcyc as shown in table 14.8. However, due to the
effect of the rise and fall times, the I²C bus interface specifications may not be satisfied at the
maximum transfer rate. Table 14.10 shows the results of calculating the output timing for each
available operating frequency, by considering the worst-case rise and fall times. t_BUFO does not
satisfy the specifications of the I²C bus interface specifications. Take either of the following
countermeasures against this problem:
A. Ensure that your program provides the required interval (approximately 1 μs) between
issuing of the stop condition and of the next start condition.
B. Select a slave device with an input timing that permits use with this output timing for
connection to the I²C bus.
Rev.4.00 Mar. 27, 2008 Page 529 of 882
REJ09B0108-0400