HD64F7144FW50V Datasheet, PDF (426/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

12. Watchdog Timer
ITI (interrupt
request signal)
WDTOVF*1
Internal reset
signal*2
Interrupt
control
Overflow
Clock
Reset
control
Clock
select
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal clock
sources
RSTCSR
TCNT
TSCR
Module bus
Bus
interface
[Legend]
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
WDT
Notes: 1. If this pin needs to be pulled-down,the resistance value must be 1MΩ or higher.
2. The internal reset signal can be generated by register setting.
Power-on reset or manual reset can be selected.
Figure 12.1 Block Diagram of WDT
12.2 Input/Output Pin
Table 12.1 shows the pin configuration.
Table 12.1 Pin Configuration
Pin
Abbreviation I/O
Watchdog timer overflow WDTOVF
Output
Function
Outputs the counter overflow signal in
watchdog timer mode
Rev.4.00 Mar. 27, 2008 Page 380 of 882
REJ09B0108-0400