HD64F7144FW50V Datasheet, PDF (546/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

14. I²C Bus Interface (IIC) Option
SCL
(Master output)
8
9
SDA
bit 0
(Master output)
Data 1
[7]
SDA
A
(Slave output)
ICDRE
IRIC
IRTR
ICDR
Data 1
1
2
3
4
5
6
7
8
9
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data 2
[10]
A
Stop condition generation
Data 2
User processing
[9] ICDR write
[9] IRIC clear
[11] ACKB read
[12] IRIC clear
[12] Write 1
to BBSY and 0
to SCP
(stop condition
issuance)
Figure 14.9 An Example of the Stop Condition Issuance Timing in Master Transmit Mode
(MLS = WAIT = 0)
Rev.4.00 Mar. 27, 2008 Page 500 of 882
REJ09B0108-0400