HD64F7144FW50V Datasheet, PDF (566/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

14. I²C Bus Interface (IIC) Option
10. When SCL is high and the stop condition is detected due to the change of SDA from low to
high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the
STOPIM bit in ICXR is 0, the IRIC flag is set to 1. When the IRIC flag is set to 1, clear the
flag to 0.
Slave receive mode
SCL
(Master output) 8
9
SDA
(Slave output)
A
[2]
SDA
(Master output) _R/W
IRIC
Slave transmit mode
1
2
3
4
5
6
7
8
9
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data 1
[4]
A
1
2
bit 7 bit 6
Data 2
ICDRE
ICDR
Data 1
Data 2
User processing
[3] IRIC clear
[3] ICDR write
[3] IRIC clear
[5] IRIC clear
[5] ICDR write
Figure 14.24 An Example of the Timing of Operations in Slave Transmit Mode (MLS = 0)
Rev.4.00 Mar. 27, 2008 Page 520 of 882
REJ09B0108-0400