HD64F7144FW50V Datasheet, PDF (555/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

14. I²C Bus Interface (IIC) Option
[8] Wait time for one cycle
Stop condition generation
SCL
(Master output)
8
9
1
2
3
4
5
6
7
8
9
SDA
bit 0
(Slave data output)
Data 2 [3]
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
[3]
Data 3
[12]
[12]
SDA
A
A
(Master output)
IRIC
IRTR
[4] IRTR=0 [4] IRTR=1
[13] IRTR=0 [13] IRTR=1
ICDR
Data 1
Data 2
Data 3
User processing
[6] IRIC clear
[11] IRIC clear
[10] ICDR read
(data 2)
[9] Set TRS to 1
[7] Set ACKB to 1
[15] Clear WAIT to 0,
[14] IRIC clear
IRIC clear
[17] Stop condition
issuance
[16] ICDR read (data 3)
Figure 14.16 An Example of the Stop Condition Issuance Timing in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)
14.4.5 Operations in Slave Reception
In the slave receive mode of the I²C bus format, the master device transmits the transmit clock and
data, and the slave device returns acknowledgements of reception. The slave device compares the
address of the slave address and the slave address of the first frame issued after the start condition
issuance by the master device. If the addresses match, the slave device operates as a slave device
specified by the master device.
Reception with HNDS Function (HNDS = 1):
Figure 14.17 is a flowchart that gives an example of operations in slave receive mode (HNDS =
1).
Rev.4.00 Mar. 27, 2008 Page 509 of 882
REJ09B0108-0400