HD64F7144FW50V Datasheet, PDF (611/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

16. Compare Match Timer (CMT)
16.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1 or the clearing
signal after the DTC transfer. Figure 16.5 shows the timing when the CMF bit is cleared by the
CPU.
CMCSR write cycle
T1 T2
Pφ
CMF
Figure 16.5 Timing of CMF Clear by CPU
Rev.4.00 Mar. 27, 2008 Page 565 of 882
REJ09B0108-0400