HD64F7144FW50V Datasheet, PDF (190/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

9. Bus State Controller (BSC)
9.5 Register Descriptions
9.5.1 Bus Control Register 1 (BCR1)
BCR1 is a 16-bit readable/writable register that enables access to the MTU control registers and
specifies the bus size of each CS space. When using the SH7144, specify the bus size as word (16-
bit) or smaller size.
Write bits 7 to 0 of BCR1 during the initialization stage after a power-on reset, and do not change
the values thereafter. In on-chip ROM enabled mode, do not access any of each CS space until
completion of register initialization. In on-chip ROM disabled mode, do not access CS spaces
other than CS0 and CS4 until completion of register initialization.
Bit Bit Name Initial Value R/W
15
⎯
0
R
14
⎯
1
R
13
MTURWE 1
R/W
12 to 8 ⎯
All 0
R
7
A3LG
0
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
MTU read/write enable
This bit enables MTU control register access. For details,
refer to section 11, Multi-Function Timer Pulse Unit
(MTU).
0: MTU control register access is disabled
1: MTU control register access is enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
CS3 and CS7 space longword
This bit specifies the CS3 and CS7 space bus size. This
bit is valid only for the SH7145.
This bit is reserved in SH7144. This bit is always read as
0 and should always be written with 0.
0: Depends on the value set with the A3SZ bit in this
register.
1: Longword (32 bits)
Rev.4.00 Mar. 27, 2008 Page 144 of 882
REJ09B0108-0400