HD64F7144FW50V Datasheet, PDF (612/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

16. Compare Match Timer (CMT)
16.5 Usage Notes
16.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
16.6 shows the timing.
CMCNT write cycle
T1 T2
Pφ
Address
Internal
write signal
Compare
match signal
CMCNT
CMCNT
N
H' 0000
Figure 16.6 CMCNT Write and Compare Match Contention
Rev.4.00 Mar. 27, 2008 Page 566 of 882
REJ09B0108-0400