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HD64F7144FW50V Datasheet, PDF (89/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 | |||
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2. CPU
⢠System Control Instructions
Instruction
Instruction Code
CLRT
0000000000001000
CLRMAC
0000000000101000
LDC Rm,SR
0100mmmm00001110
LDC Rm,GBR 0100mmmm00011110
LDC Rm,VBR 0100mmmm00101110
LDC.L @Rm+,SR 0100mmmm00000111
LDC.L @Rm+,GBR 0100mmmm00010111
LDC.L @Rm+,VBR 0100mmmm00100111
LDS Rm,MACH 0100mmmm00001010
LDS Rm,MACL 0100mmmm00011010
LDS Rm,PR
0100mmmm00101010
LDS.L @Rm+,MACH 0100mmmm00000110
LDS.L @Rm+,MACL 0100mmmm00010110
LDS.L @Rm+,PR 0100mmmm00100110
NOP
0000000000001001
RTE
0000000000101011
SETT
0000000000011000
SLEEP
0000000000011011
STC SR,Rn
0000nnnn00000010
STC GBR,Rn 0000nnnn00010010
STC VBR,Rn 0000nnnn00100010
STC.L SR,@âRn 0100nnnn00000011
STC.L GBR,@âRn 0100nnnn00010011
STC.L VBR,@âRn 0100nnnn00100011
STS MACH,Rn 0000nnnn00001010
STS MACL,Rn 0000nnnn00011010
STS PR,Rn
0000nnnn00101010
STS.L MACH,@âRn 0100nnnn00000010
STS.L MACL,@âRn 0100nnnn00010010
STS.L PR,@âRn 0100nnnn00100010
Operation
0âT
0 â MACH, MACL
Rm â SR
Rm â GBR
Rm â VBR
(Rm) â SR, Rm + 4 â Rm
(Rm) â GBR, Rm + 4 â Rm
(Rm) â VBR, Rm + 4 â Rm
Rm â MACH
Rm â MACL
Rm â PR
(Rm) â MACH, Rm + 4 â Rm
(Rm) â MACL, Rm + 4 â Rm
(Rm) â PR, Rm + 4 â Rm
No operation
Delayed branch, stack area
â PC/SR
1âT
Sleep
SR â Rn
GBR â Rn
VBR â Rn
Rn â 4 â Rn, SR â (Rn)
Rn â 4 â Rn, GBR â (Rn)
Rn â 4 â Rn, BR â (Rn)
MACH â Rn
MACL â Rn
PR â Rn
Rn â 4 â Rn, MACH â (Rn)
Rn â 4 â Rn, MACL â (Rn)
Rn â 4 â Rn, PR â (Rn)
Execution
States T Bit
1
0
1
â
1
LSB
1
â
1
â
3
LSB
3
â
3
â
1
â
1
â
1
â
1
â
1
â
1
â
1
â
4
â
1
1
3*
â
1
â
1
â
1
â
2
â
2
â
2
â
1
â
1
â
1
â
1
â
1
â
1
â
Rev.4.00 Mar. 27, 2008 Page 43 of 882
REJ09B0108-0400
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