HD64F7144FW50V Datasheet, PDF (834/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

26. Electrical Characteristics
26.3.10 I²C Bus Interface Timing
Table 26.12 shows I²C bus interface timing.
Table 26.12 I²C Bus Interface Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Symbol Min.
Typ. Max.
Unit Figure
SCL input cycle time
t
SCL
SCL input high pulse width t_SCLH
SCL input low pulse width
t_SCLL
SCL and SDA input rise time t_Sr
SCL and SDA input fall time t_Sf
SCL and SDA input spike
t_SP
pulse removal time
12
t *1
pcyc
⎯
⎯
ns
3 t_pcyc
⎯⎯
ns
5 t_pcyc
⎯⎯
ns
⎯
⎯
7.5
t *2
pcyc
ns
⎯
⎯ 300
ns
⎯
⎯
1 t_pcyc
ns
Figure 26.21
SDA input bus free time
t
5t
⎯⎯
ns
BUF
pcyc
Start condition input hold time t
3t
⎯⎯
ns
STAH
pcyc
Retransmission start
t
3t
⎯⎯
ns
STAS
pcyc
condition input setup time
Halt condition input setup
t_STOS
3 t_pcyc
⎯⎯
ns
time
Data input setup time
t_SDAS
35
⎯⎯
ns
Data input hold time
t_SDAH
0
⎯⎯
ns
SCL and SDA capacity load C
⎯
b
⎯ 400
pF
Notes: 1. t (ns) = 1/(Pφ supplied to I2C module (MHz) )
pcyc
2. Can be set to 17.5 t_pcyc by selecting the clock to be used for the I²C module. For details,
refer to section 14.5, Usage Notes.
Rev.4.00 Mar. 27, 2008 Page 788 of 882
REJ09B0108-0400