HD64F7144FW50V Datasheet, PDF (523/932 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144

14. I²C Bus Interface (IIC) Option
14.3.5 I²C Bus Control Register (ICCR)
ICCR controls I²C bus interface and confirms the state of interrupt flag.
Bit Bit Name Initial Value R/W Description
7 ICE
0
R/W I²C Bus Interface Enable
0: This module is not operating.
The internal state of the I²C module is cleared.
Access to SAR and SARX is enabled.
1: This module is in its transfer-enabled state
6 IEIC
0
R/W I²C Bus Interface Interrupt Enable
0: Disables the interrupt from the I²C bus interface to
the CPU
1: Enables the interrupt from the I²C bus interface to the
CPU
Rev.4.00 Mar. 27, 2008 Page 477 of 882
REJ09B0108-0400